South Korea’s tech giant Samsung Electronics Co. plans to actively respond to the growing demand for customized high-bandwidth memory (HBM) in the era of artificial intelligence (AI).

“In the early HBM market, hardware versatility was crucial, but as services mature around killer apps moving forward, hardware infrastructure will inevitably undergo a process of optimization for each service,” said Kim Kyung-ryun, vice president of memory product planning at Samsung Electronics. “We plan to unify core dies for data storage and diversify package and base dies to accommodate these changes.”

His remarks were made in an in-house interview posted on Samsung Newsroom on Thursday. Kim was joined by Youn Jae-youn, vice president of DRAM development at Samsung Electronics‘ Device Solutions (DS) division.

“The need for joint optimization will increase the demand for customization, and we will maximize common design elements through platformization and create a system that can efficiently respond to customization needs by expanding the ecosystem of partners,” Kim said.

The vice president also noted an industry consensus that processor and memory companies individually optimizing products could find it difficult to create future innovations demanded by the era of general artificial intelligence (AGI).

He stressed that “custom HBM is a bridgehead to the AGI era.”

“Samsung will respond with its comprehensive capabilities in memory, foundry, system LSI, and advanced packaging (AVP),” Kim said. “We have also formed a dedicated team for next-generation HBMs, which will be unrivaled in the industry and will have significant effects.”

Samsung Electronics successfully developed the industry’s largest 12-layer HBM3E 12H DRAM with a capacity of 36 gigabytes (GB) in February 2024.

Youn introduced the chip as ”a product with the world’s highest specifications in terms of speed and capacity,” highlighting the unique competitive advantage of the advanced ‘thermal compression non-conductive film (TC-NCF) technology’ in heat dissipation for HBM.

“The thermal resistance of HBM is mainly influenced by the chip spacing, and we have reduced the thickness of the NCF material applied between the chips and enhanced the chip control technology in high-density stacking, while reducing chip spacing through thermal compression technology,” Youn said.

Kim anticipated that 36GB HBM3E 12H DRAM, with a capacity 2.25 times larger than the current market’s leader, 16GB HBM3 8H, will quickly become a mainstream product once it is commercialized.

“The product has the effect of reducing the total cost of ownership (TCO) as it allows the same large language model (LLM) to be serviced with fewer AI servers than before, which is why our customers have high expectations of the product,” he said.

By Pulse

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